﻿#include "CpuOpCodes.h"

//|      12    11    10    | 9   8      7      6  | 5        4        3        2 |        | 1        0 |
//|        opCycles    |    Reserved    |           Address mode          |        | opBytes |        



//    uint16_t      mnemonic:6; reserve :1; opBytes :2; opCycles:3; addrMode:4;

const CpuDecodeTable_t cpuDecodeTable[] =
{
/*0x00*/ { BRK,   0,   0,   1,   7,   IMPL_ADDR_MODE },
/*0x01*/ { ORA,   0,   1,   2,   6,   IND_X_ADDR_MODE },
/*0x02*/ {   0,   0,   0,   0,   0,   0 },
/*0x03*/ {   0,   0,   0,   0,   0,   0 },
/*0x04*/ {   0,   0,   0,   0,   0,   0 },
/*0x05*/ { ORA,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0x06*/ { ASL,   1,   1,   2,   5,   ZP_ADDR_MODE },
/*0x07*/ {   0,   0,   0,   0,   0,   0 },
/*0x08*/ { PHP,   0,   0,   1,   3,   IMPL_ADDR_MODE },
/*0x09*/ { ORA,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0x0A*/ { ASL,   1,   1,   1,   2,   ACC_ADDR_MODE },
/*0x0B*/ {   0,   0,   0,   0,   0,   0 },
/*0x0C*/ {   0,   0,   0,   0,   0,   0 },
/*0x0D*/ { ORA,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0x0E*/ { ASL,   1,   1,   3,   6,   ABS_ADDR_MODE },
/*0x0F*/ {   0,   0,   0,   0,   0,   0 },
/*0x10*/ { BPL,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0x11*/ { ORA,   0,   1,   2,   5,   IND_Y_ADDR_MODE },
/*0x12*/ { ORA,   0,   1,   2,   4,   ZP_ADDR_MODE },
/*0x13*/ {   0,   0,   0,   0,   0,   0 },
/*0x14*/ {   0,   0,   0,   0,   0,   0 },
/*0x15*/ { ORA,   0,   1,   2,   4,   ZP_X_ADDR_MODE }, 
/*0x16*/ { ASL,   1,   1,   2,   6,   ZP_X_ADDR_MODE },
/*0x17*/ {   0,   0,   0,   0,   0,   0 },
/*0x18*/ { CLC,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x19*/ { ORA,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0x1A*/ {   0,   0,   0,   0,   0,   0 },
/*0x1B*/ {   0,   0,   0,   0,   0,   0 },
/*0x1C*/ {   0,   0,   0,   0,   0,   0 },
/*0x1D*/ { ORA,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0x1E*/ { ASL,   1,   1,   3,   7,   ABS_X_ADDR_MODE },
/*0x1F*/ {   0,   0,   0,   0,   0,   0 },
/*0x20*/ { JSR,   0,   0,   3,   6,   ABS_ADDR_MODE },
/*0x21*/ { AND,   0,   1,   2,   6,   IND_X_ADDR_MODE },
/*0x22*/ {   0,   0,   0,   0,   0,   0 },
/*0x23*/ {   0,   0,   0,   0,   0,   0 },
/*0x24*/ { BIT,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0x25*/ { AND,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0x26*/ { ROL,   1,   1,   2,   5,   ZP_ADDR_MODE },
/*0x27*/ {   0,   0,   0,   0,   0,   0 },
/*0x28*/ { PLP,   0,   0,   1,   4,   IMPL_ADDR_MODE },
/*0x29*/ { AND,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0x2A*/ { ROL,   1,   1,   1,   2,   ACC_ADDR_MODE },
/*0x2B*/ {   0,   0,   0,   0,   0,   0 },
/*0x2C*/ { BIT,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0x2D*/ { AND,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0x2E*/ { ROL,   1,   1,   3,   6,   ABS_ADDR_MODE },
/*0x2F*/ {   0,   0,   0,   0,   0,   0 },
/*0x30*/ { BMI,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0x31*/ { AND,   0,   1,   2,   5,   IND_Y_ADDR_MODE },
/*0x32*/ {   0,   0,   0,   0,   0,   0 },
/*0x33*/ {   0,   0,   0,   0,   0,   0 },
/*0x34*/ {   0,   0,   0,   0,   0,   0 },
/*0x35*/ { AND,   0,   1,   2,   4,   ZP_X_ADDR_MODE },
/*0x36*/ { ROL,   1,   1,   2,   6,   ZP_X_ADDR_MODE },
/*0x37*/ {   0,   0,   0,   0,   0,   0 },
/*0x38*/ { SEC,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x39*/ { AND,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0x3A*/ {   0,   0,   0,   0,   0,   0 },
/*0x3B*/ {   0,   0,   0,   0,   0,   0 },
/*0x3C*/ {   0,   0,   0,   0,   0,   0 },
/*0x3D*/ { AND,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0x3E*/ { ROL,   1,   1,   3,   7,   ABS_X_ADDR_MODE },
/*0x3F*/ {   0,   0,   0,   0,   0,   0 },
/*0x40*/ { RTI,   0,   0,   1,   6,   IMPL_ADDR_MODE },
/*0x41*/ { EOR,   0,   1,   2,   6,   IND_X_ADDR_MODE },
/*0x42*/ {   0,   0,   0,   0,   0,   0 },
/*0x43*/ {   0,   0,   0,   0,   0,   0 },
/*0x44*/ {   0,   0,   0,   0,   0,   0 },
/*0x45*/ { EOR,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0x46*/ { LSR,   1,   1,   2,   5,   ZP_ADDR_MODE },
/*0x47*/ {   0,   0,   0,   0,   0,   0 },
/*0x48*/ { PHA,   0,   0,   1,   3,   IMPL_ADDR_MODE },
/*0x49*/ { EOR,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0x4A*/ { LSR,   1,   1,   1,   2,   ACC_ADDR_MODE },
/*0x4B*/ {   0,   0,   0,   0,   0,   0 },
/*0x4C*/ { JMP,   0,   0,   3,   3,   ABS_ADDR_MODE },
/*0x4D*/ { EOR,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0x4E*/ { LSR,   1,   1,   3,   6,   ABS_ADDR_MODE },
/*0x4F*/ {   0,   0,   0,   0,   0,   0 },
/*0x50*/ { BVC,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0x51*/ { EOR,   0,   1,   2,   5,   IND_Y_ADDR_MODE },
/*0x52*/ {   0,   0,   0,   0,   0,   0 },
/*0x53*/ {   0,   0,   0,   0,   0,   0 },
/*0x54*/ {   0,   0,   0,   0,   0,   0 },
/*0x55*/ { EOR,   0,   1,   2,   4,   ZP_X_ADDR_MODE },
/*0x56*/ { LSR,   1,   1,   2,   6,   ZP_X_ADDR_MODE },
/*0x57*/ {   0,   0,   0,   0,   0,   0 },
/*0x58*/ { CLI,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x59*/ { EOR,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0x5A*/ {   0,   0,   0,   0,   0,   0 },
/*0x5B*/ {   0,   0,   0,   0,   0,   0 },
/*0x5C*/ {   0,   0,   0,   0,   0,   0 },
/*0x5D*/ { EOR,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0x5E*/ { LSR,   1,   1,   3,   7,   ABS_X_ADDR_MODE },
/*0x5F*/ {   0,   0,   0,   0,   0,   0 },
/*0x60*/ { RTS,   0,   0,   1,   6,   IMPL_ADDR_MODE },
/*0x61*/ { ADC,   0,   1,   2,   6,   IND_X_ADDR_MODE },
/*0x62*/ {   0,   0,   0,   0,   0,   0 },
/*0x63*/ {   0,   0,   0,   0,   0,   0 },
/*0x64*/ {   0,   0,   0,   0,   0,   0 },
/*0x65*/ { ADC,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0x66*/ { ROR,   1,   1,   2,   5,   ZP_ADDR_MODE },
/*0x67*/ {   0,   0,   0,   0,   0,   0 },
/*0x68*/ { PLA,   0,   0,   1,   4,   IMPL_ADDR_MODE },
/*0x69*/ { ADC,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0x6A*/ { ROR,   1,   1,   1,   2,   ACC_ADDR_MODE },
/*0x6B*/ {   0,   0,   0,   0,   0,   0 },
/*0x6C*/ { JMP,   0,   0,   3,   5,   IND_ADDR_MODE },
/*0x6D*/ { ADC,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0x6E*/ { ROR,   1,   1,   3,   6,   ABS_ADDR_MODE },
/*0x6F*/ {   0,   0,   0,   0,   0,   0 },
/*0x70*/ { BVS,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0x71*/ { ADC,   0,   1,   2,   5,   IND_Y_ADDR_MODE },
/*0x72*/ {   0,   0,   0,   0,   0,   0 },
/*0x73*/ {   0,   0,   0,   0,   0,   0 },
/*0x74*/ {   0,   0,   0,   0,   0,   0 },
/*0x75*/ { ADC,   0,   1,   2,   4,   ZP_X_ADDR_MODE },
/*0x76*/ { ROR,   1,   1,   2,   6,   ZP_X_ADDR_MODE },
/*0x77*/ {   0,   0,   0,   0,   0,   0 },
/*0x78*/ { SEI,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x79*/ { ADC,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0x7A*/ {   0,   0,   0,   0,   0,   0 },
/*0x7B*/ {   0,   0,   0,   0,   0,   0 },
/*0x7C*/ {   0,   0,   0,   0,   0,   0 },
/*0x7D*/ { ADC,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0x7E*/ { ROR,   1,   1,   3,   7,   ABS_X_ADDR_MODE },
/*0x7F*/ {   0,   0,   0,   0,   0,   0 },
/*0x80*/ {   0,   0,   0,   0,   0,   0 },
/*0x81*/ { STA,   1,   0,   2,   6,   IND_X_ADDR_MODE },
/*0x82*/ {   0,   0,   0,   0,   0,   0 },
/*0x83*/ {   0,   0,   0,   0,   0,   0 },
/*0x84*/ { STY,   1,   0,   2,   3,   ZP_ADDR_MODE },
/*0x85*/ { STA,   1,   0,   2,   3,   ZP_ADDR_MODE },
/*0x86*/ { STX,   1,   0,   2,   3,   ZP_ADDR_MODE },
/*0x87*/ {   0,   0,   0,   0,   0,   0 },
/*0x88*/ { DEY,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x89*/ {   0,   0,   0,   0,   0,   0 },
/*0x8A*/ { TXA,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x8B*/ {   0,   0,   0,   0,   0,   0 },
/*0x8C*/ { STY,   1,   0,   3,   4,   ABS_ADDR_MODE },
/*0x8D*/ { STA,   1,   0,   3,   4,   ABS_ADDR_MODE },
/*0x8E*/ { STX,   1,   0,   3,   4,   ABS_ADDR_MODE },
/*0x8F*/ {   0,   0,   0,   0,   0,   0 },
/*0x90*/ { BCC,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0x91*/ { STA,   1,   0,   2,   6,   IND_Y_ADDR_MODE },
/*0x92*/ {   0,   0,   0,   0,   0,   0 },
/*0x93*/ {   0,   0,   0,   0,   0,   0 },
/*0x94*/ { STY,   1,   0,   2,   4,   ZP_X_ADDR_MODE },
/*0x95*/ { STA,   1,   0,   2,   4,   ZP_X_ADDR_MODE },
/*0x96*/ { STX,   1,   0,   2,   4,   ZP_Y_ADDR_MODE },
/*0x97*/ {   0,   0,   0,   0,   0,   0 },
/*0x98*/ { TYA,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x99*/ { STA,   1,   0,   3,   5,   ABS_Y_ADDR_MODE },
/*0x9A*/ { TXS,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0x9B*/ {   0,   0,   0,   0,   0,   0 },
/*0x9C*/ {   0,   0,   0,   0,   0,   0 },
/*0x9D*/ { STA,   1,   0,   3,   5,   ABS_X_ADDR_MODE },
/*0x9E*/ {   0,   0,   0,   0,   0,   0 },
/*0x9F*/ {   0,   0,   0,   0,   0,   0 },
/*0xA0*/ { LDY,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0xA1*/ { LDA,   0,   1,   2,   6,   IND_X_ADDR_MODE },
/*0xA2*/ { LDX,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0xA3*/ {   0,   0,   0,   0,   0,   0 },
/*0xA4*/ { LDY,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0xA5*/ { LDA,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0xA6*/ { LDX,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0xA7*/ {   0,   0,   0,   0,   0,   0 },
/*0xA8*/ { TAY,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xA9*/ { LDA,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0xAA*/ { TAX,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xAB*/ {   0,   0,   0,   0,   0,   0 },
/*0xAC*/ { LDY,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0xAD*/ { LDA,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0xAE*/ { LDX,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0xAF*/ {   0,   0,   0,   0,   0,   0 },
/*0xB0*/ { BCS,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0xB1*/ { LDA,   0,   1,   2,   5,   IND_Y_ADDR_MODE },
/*0xB2*/ {   0,   0,   0,   0,   0,   0 },
/*0xB3*/ {   0,   0,   0,   0,   0,   0 },
/*0xB4*/ { LDY,   0,   1,   2,   4,   ZP_X_ADDR_MODE },
/*0xB5*/ { LDA,   0,   1,   2,   4,   ZP_X_ADDR_MODE },
/*0xB6*/ { LDX,   0,   1,   2,   4,   ZP_Y_ADDR_MODE },
/*0xB7*/ {   0,   0,   0,   0,   0,   0 },
/*0xB8*/ { CLV,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xB9*/ { LDA,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0xBA*/ { TSX,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xBB*/ {   0,   0,   0,   0,   0,   0 },
/*0xBC*/ { LDY,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0xBD*/ { LDA,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0xBE*/ { LDX,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0xBF*/ {   0,   0,   0,   0,   0,   0 },
/*0xC0*/ { CPY,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0xC1*/ { CMP,   0,   1,   2,   6,   IND_X_ADDR_MODE },
/*0xC2*/ {   0,   0,   0,   0,   0,   0 },
/*0xC3*/ {   0,   0,   0,   0,   0,   0 },
/*0xC4*/ { CPY,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0xC5*/ { CMP,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0xC6*/ { DEC,   1,   1,   2,   5,   ZP_ADDR_MODE },
/*0xC7*/ {   0,   0,   0,   0,   0,   0 },
/*0xC8*/ { INY,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xC9*/ { CMP,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0xCA*/ { DEX,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xCB*/ {   0,   0,   0,   0,   0,   0 },
/*0xCC*/ { CPY,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0xCD*/ { CMP,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0xCE*/ { DEC,   1,   1,   3,   6,   ABS_ADDR_MODE },
/*0xCF*/ {   0,   0,   0,   0,   0,   0 },
/*0xD0*/ { BNE,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0xD1*/ { CMP,   0,   1,   2,   5,   IND_Y_ADDR_MODE },
/*0xD2*/ {   0,   0,   0,   0,   0,   0 },
/*0xD3*/ {   0,   0,   0,   0,   0,   0 },
/*0xD4*/ {   0,   0,   0,   0,   0,   0 },
/*0xD5*/ { CMP,   0,   1,   2,   4,   ZP_X_ADDR_MODE },
/*0xD6*/ { DEC,   1,   1,   2,   6,   ZP_X_ADDR_MODE },
/*0xD7*/ {   0,   0,   0,   0,   0,   0 },
/*0xD8*/ { CLD,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xD9*/ { CMP,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0xDA*/ {   0,   0,   0,   0,   0,   0 },
/*0xDB*/ {   0,   0,   0,   0,   0,   0 },
/*0xDC*/ {   0,   0,   0,   0,   0,   0 },
/*0xDD*/ { CMP,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0xDE*/ { DEC,   1,   1,   3,   7,   ABS_X_ADDR_MODE },
/*0xDF*/ {   0,   0,   0,   0,   0,   0 },
/*0xE0*/ { CPX,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0xE1*/ { SBC,   0,   1,   2,   6,   IND_X_ADDR_MODE },
/*0xE2*/ {   0,   0,   0,   0,   0,   0 },
/*0xE3*/ {   0,   0,   0,   0,   0,   0 },
/*0xE4*/ { CPX,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0xE5*/ { SBC,   0,   1,   2,   3,   ZP_ADDR_MODE },
/*0xE6*/ { INC,   1,   1,   2,   5,   ZP_ADDR_MODE },
/*0xE7*/ {   0,   0,   0,   0,   0,   0 },
/*0xE8*/ { INX,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xE9*/ { SBC,   0,   1,   2,   2,   IMM_ADDR_MODE },
/*0xEA*/ { NOP,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xEB*/ {   0,   0,   0,   0,   0,   0 },
/*0xEC*/ { CPX,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0xED*/ { SBC,   0,   1,   3,   4,   ABS_ADDR_MODE },
/*0xEE*/ { INC,   1,   1,   3,   6,   ABS_ADDR_MODE },
/*0xEF*/ {   0,   0,   0,   0,   0,   0 },
/*0xF0*/ { BEQ,   0,   0,   2,   2,   REL_ADDR_MODE },
/*0xF1*/ { SBC,   0,   1,   2,   5,   IND_Y_ADDR_MODE },
/*0xF2*/ {   0,   0,   0,   0,   0,   0 },
/*0xF3*/ {   0,   0,   0,   0,   0,   0 },
/*0xF4*/ {   0,   0,   0,   0,   0,   0 },
/*0xF5*/ { SBC,   0,   1,   2,   4,   ZP_X_ADDR_MODE },
/*0xF6*/ { INC,   1,   1,   2,   6,   ZP_X_ADDR_MODE },
/*0xF7*/ {   0,   0,   0,   0,   0,   0 },
/*0xF8*/ { SED,   0,   0,   1,   2,   IMPL_ADDR_MODE },
/*0xF9*/ { SBC,   0,   1,   3,   4,   ABS_Y_ADDR_MODE },
/*0xFA*/ {   0,   0,   0,   0,   0,   0 },
/*0xFB*/ {   0,   0,   0,   0,   0,   0 },
/*0xFC*/ {   0,   0,   0,   0,   0,   0 },
/*0xFD*/ { SBC,   0,   1,   3,   4,   ABS_X_ADDR_MODE },
/*0xFE*/ { INC,   1,   1,   3,   7,   ABS_X_ADDR_MODE },
};

